Point-to-point communication between electronic devices, such as integrated circuits (“ICs”), is generally considered to be reliable, especially when a dedicated synchronous clock line is used to synchronize data transfers. In particular, many system designers expect communications between ICs to conform to a prevailing assumption that data bits exchanged between ICs are the same data bits. For example, most conventional processor ICs are designed to act upon data fetched from a memory IC regardless of whether either the address bits transmitted to the memory IC were correctly received, or the data received by the processor IC were the same as sent by the memory IC. But with traditional physical interfaces both transmitting data bits at faster data rates and at decreasing amplitudes (i.e., decreasing transmission power), the effects of background noise on the strength of the data signals causes the signal-to-noise ratios to decrease, which is indicative of an increase in errors that could thwart reliable point-to-point communications. Further, many system designers are implementing physical interfaces that serially transport data over a serial data link using asynchronous clocking techniques, whereby the clock is embedded in encoded serialized data. Examples of high-speed serial communications technologies having serial data links include Serial ATA (“SATA”)®, Transition Minimized Differential Signaling (“TMDS”), PCI Express, InfiniBand®, and the like. While conventional physical interfaces that provide for serial data communications reduce both noise and power, at least one drawback is that conventional serial data links are susceptible to data corruption during transit.
In the field of computer networking, the Open Systems Interconnect (“OSI”) model describes a common approach to detect and correct errors between two end stations (or computing devices). According to this approach, a data link layer calculates an error-detecting code (e.g., a cyclic redundancy code, “CRC”) based on a frame of transmitted bits. Then, it appends the error-detecting code as contiguous bits to the frame and then passes both the error-detecting code and the application data bits to a physical interface for line encoding (or coding). One example of line encoding translates 8 application data bits into 10 encoded bits. This type of line encoding technique is commonly known as 8B/10B. After line encoding is performed, the serial physical interface drives the encoded bits out over a communications medium to another serial physical interface, which recovers the clock and decodes the bits. The data link layer at the receiver then applies error detection and correction techniques using the contiguous bits of error-detecting code.
While functional, the data link layer performs these error detection and correction processes beyond the physical interface, thereby delaying error detection and/or resolution. Also, conventional physical interfaces are generally not well suited to facilitate error detection and correction in a standardized manner. For example, traditional physical interfaces are optimized to provide synchronous and parallel data communications between integrated circuits. As such, they can not readily be adapted to provide timely and reliable data transfers for asynchronous and serial data communications, such as over a serial data link. Further, conventional physical interfaces are not generally conducive to at least provide: (1) transparent error detection and recovery techniques that do not require an application to participate in specialized error handling techniques, and (2) efficient transmissions of error detection codes to increase the rate that those codes are transferred over the serial data link.
In view of the foregoing, it would be desirable to provide a physical interface, an apparatus and a method that minimize the above-mentioned drawbacks and provides for at least error detection and optional error recovery.